The present invention relates generally to semiconductor device manufacturing and more particularly to methods of manufacturing flash memory devices.
Flash memory devices are a type of EEPROM (Electrically Erasable to Programmable Read-Only Memory). The term xe2x80x9cflashxe2x80x9d refers to the ability of the memory to be erased in blocks. Flash memory devices typically include multiple individual components formed on or within a substrate. Such devices often comprise a high density section and a low density section. For example, as illustrated in prior art FIG. 1A, a memory device such as a flash memory 10 comprises one or more high density core regions 11 and a low density peripheral portion 12 on a single substrate 13. The high density core regions 11 typically consist of at least one MxN array of individually addressable, substantially identical floating-gate type memory cells and the low density peripheral portion 12 typically includes input/output (I/O) circuitry and circuitry for selectively addressing the individual cells (such as decoders for connecting the source, gate and drain of selected cells to predetermined voltages or impedances to affect designated operations of the cell such as programming, reading or erasing).
While there are myriad ways of configuring flash memory devices, in one common configuration sometimes called a NOR architecture, the drain regions of each memory cell (transistor) have a contact and are connected in rows forming bit lines, for example, the configuration illustrated in prior art FIG. 1B. Each memory cell 14 has a drain 14a, a source 14b and a stacked gate 14c. 
The NOR configuration illustrated in FIG. 1B has each drain terminal 14a of the transistors within a single column connected to the same bit line (BL). In addition, each flash cell 14 has its stacked gate terminal 14c coupled to a different word line (WL) while all the flash cells in the array have their source terminals 14b coupled to a common source terminal (CS). In operation, individual flash cells may be individually addressed via the respective bit line and word line using peripheral decoder and control circuitry for programming (writing), reading or erasing functions.
Prior art FIG. 2 represents a fragmentary cross section diagram of a typical memory cell 14 in the core region 11 of prior art FIGS. 1A and 1B. Such a cell 14 typically includes the source 14b, the drain 14a, and a channel 15 in a substrate or P-well 16; and the stacked gate structure 14c overlying the channel 15. The stacked gate 14c further includes a thin gate dielectric layer 17a (commonly referred to as the tunnel oxide) formed on the surface of the P-well 16. The stacked gate 14c also includes a polysilicon floating gate 17b which overlies the tunnel oxide 17a and an interpoly dielectric layer 17c overlies the floating gate 17b. The interpoly dielectric layer 17c is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers sandwiching a nitride layer. Lastly, a polysilicon control gate 17d overlies the interpoly dielectric layer 17c. The control gates 17d of the respective cells 14 that are formed in a lateral row share a common word line (WL) associated with the row of cells (see, e.g., prior art FIG. 1B). In addition, as highlighted above, the drain regions 14a of the respective cells in a vertical column are connected together by a conductive bit line (BL). The channel 15 of the cell 14 conducts current between the source 14b and the drain 14a in accordance with an electric field developed in the channel 15 by the stacked gate structure 14c. 
According to conventional operation, the flash memory cell 14 operates in the following manner. The cell 14 is programmed by applying a relatively high voltage VG (e.g., approximately 9 volts) to the control gate 17d and connecting the source to ground and the drain 14a to a predetermined potential above the source 14b (e.g., approximately 5 volts). These voltages generate a vertical and lateral electric field along the length of the channel from the source to the drain. This electric field causes electrons to be drawn off the source and begin accelerating toward the drain. As they move along the length of the channel, they gain energy. If they gain enough energy, they are able to jump over the potential barrier of the oxide into the floating gate 17b and become trapped in the floating gate 17b since the floating gate 17b is surrounded by insulators (the interpoly dielectric 17c and the tunnel oxide 17a). As a result of the trapped electrons, the threshold voltage of the cell 14 increases, for example, by about 2 to 5 volts. This change in the threshold voltage (and thereby the channel conductance) of the cell 14 created by the trapped electrons is what causes the cell to be programmed.
To read the memory cell 14, a predetermined voltage VG that is greater than the threshold voltage of an unprogrammed or erased cell, but less than the threshold voltage of a programmed cell, is applied to the control gate 17d with a voltage applied between the source 14b and the drain 14a (e.g., tying the source 14b to ground and applying about 1-2 volts to the drain 14a). If the cell 14 conducts (e.g., about 50-100 xcexcA), then the cell 14 has not been programmed (the cell 14 is therefore at a first logic state, e.g., a zero xe2x80x9c0xe2x80x9d). Likewise, if the cell 14 does not conduct (e.g., considerably less current than 50-100 xcexcA), then the cell 14 has been programmed (the cell 14 is therefore at a second logic state, e.g., a one xe2x80x9c1xe2x80x9d). Consequently, one can read each cell 14 to determine whether it has been programmed (and therefore identify its logic state).
A flash memory cell 14 can be erased in a number of ways. In one arrangement, a relatively high voltage Vs (e.g., approximately 12-20 volts) is applied to the source 14b and the control gate 17d is held at a ground potential (VG=0), while the drain 14a is allowed to float. Under these conditions, a strong electric field is developed across the tunnel oxide 17a between the floating gate 17b and the source 14b. The electrons that are trapped in the floating gate undergo Fowler-Nordheim tunneling through the tunnel oxide 17a to the source 14b. In another arrangement, applying a negative voltage on the order of minus 10 volts to the control gate, applying 5 volts to the source and allowing the drain to float can also erase a cell. In a further arrangement, applying 5 volts to the P-well and minus 10 volts to the control gate while allowing the source and drain to float erases a cell.
In the NOR memory architecture of prior art FIG. 1B, the drain regions of cells along a given bit line are connected together via a conductive layer and contacts. The conductive layer can be, for example, a first metal layer. Source regions are typically connected by Vss or common source (CS) lines running parallel to the word lines and leading to a common ground. The Vss lines are formed typically by doping the semiconductor substrate. This NOR-type configuration has proven useful in building compact, high-speed flash memory devices, however, there has been a continuous demand to further reduce the size of these devices. In further reducing the size of flash memory devices, the resistance associated with the Vss lines has become an issue.
Various solutions employed to lower the Vss resistance have some undesirable consequences. For example, in order to form the Vss region via ion implantation, the field oxide regions (e.g., formed via either LOCOS or STI) that traverse the word lines (in the bit line direction) must be removed in those regions associated with the source regions of the cells. For example, as illustrated in prior art FIG. 3, the field oxide regions 30 (illustrated in this example as shallow trench isolation) extend in a bit line direction 32 and traverse two word line stacks 34 residing on a substrate 36, and are modestly thick (e.g., about 3,000 Angstroms) and therefore the removal thereof requires a substantially heavy etch. The etch process employed to remove the field oxide regions 30 is often referred to as a self-aligned source (SAS) etch and occurs subsequent to the stacked gate etch (SGE) which defines the memory cell stacks 34 along a given word line. The SAS etch is relatively heavy to remove the substantially thick field oxide regions in source regions 38, as illustrated in prior art FIG. 4, and consequently may tend to damage undesirably the sidewalls of the stacked gates.
In addition, as illustrated in prior art FIG. 5A, once the SAS etch has removed the field oxide regions 30 to expose the Vss regions along respective word lines, a Vss core implant (VCI) is performed to form a relatively low resistance Vss line thereat. The Vss region 38, however, is not planar due to the etched field oxide regions, as illustrated in FIG. 5A, and therefore in order to minimize the resistance of the Vss line, the VCI implant typically comprises three separate implant steps, wherein a generally vertical, and two angled implants are performed in order to uniformly dope the Vss region, as illustrated in prior art FIGS. 5A and 5B. Such multiple implants increase the complexity of the process and reduce throughput undesirably. In addition, the resistivity of the heavily doped areas are still relatively resistive and thus different source regions may reside at different potentials and such variations may have an adverse impact on memory operations. Thus, there has been an unsatisfied need for methods of further reducing the Vss or common source resistance in NOR-type flash memory devices.
The following presents a simplified summary of the invention in order to provide a basic understanding of some of its aspects. This summary is not an extensive overview of the invention and is intended neither to identify key or critical elements of the invention nor to delineate its scope. The primary purpose of this summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
One aspect of the invention relates to a method of manufacturing a NOR-type flash memory device wherein the array of memory cells arc arranged to have each source region (or at least a plurality of source regions) coupled together to form a common source. The method allows for the common source resistance to be decreased substantially while concurrently permitting a reduction in the word line-to-word line spacing.
The method comprises forming the array of memory cells and then covering the array with a first portion of an initial dielectric covering layer (e.g., ILD0). Contact holes are then formed down to the source regions, and a plurality of trenches are formed therein which extend between a plurality of the source contact holes, each along a given word line. Upon filling the contact holes and trenches with a conductive material such as metal, the source regions of cells along a given word line are electrically coupled together. Because the trenches may reside in the top portion of the initial dielectric covering layer above the memory cells, the trenches may have a substantial volume, thereby allowing the source line (e.g., Vss or common source) resistance to be extremely small without requiring additional area between word lines.
The method further comprises forming a second portion of the initial dielectric covering layer over the first dielectric portion, the filled contact holes and the filled trenches. Contact holes are then be formed through the first and second portions of the initial dielectric layer down to the drain regions of the memory cells, and a conductive material fills the contact holes to facilitate electrical contact thereto. Additional dielectric layers (e.g., ILD1) are then formed over the device and wiring patterns are formed therein to connect the drains of the cells to other cells and/or other circuitry as desired.
The present invention advantageously allows for the elimination of a self-aligned source (SAS) etch which was conventionally performed to remove isolation regions between source regions along a given word line. In addition, because each source region is coupled together via contacts and a conductive trench, multiple high dose implant steps which were conventionally employed to form a low resistance Vss are avoided, thereby reducing the complexity of the process. In addition, the present invention is equally applicable for different types of flash memory cells types such as stacked gate cells or SONOS type cells. Lastly, although the present invention is certainly advantageous for NOR-type architectures in which all the source regions are coupled together in a given sector or the entire core region, the present invention also finds applicability in other type architectures in which multiple source regions are to be connected together and a low resistance connection is desired.
According to still another aspect of the present invention, a NOR-type flash memory structure is disclosed. The memory structure comprises an array of memory cells arranged as columns of bit lines with rows of word lines traversing the bit lines. A first portion of an initial dielectric layer overlies the array and a plurality of source contact vias extend to source regions associated with cells in the array. The source contact vias are filled with conductive material such as metal and conductive lines couple the source regions together.
In one aspect, the conductive lines reside in trenches formed within the first portion of the dielectric layer, while in another aspect the conductive lines are formed on a top surface thereof. A second portion of the initial dielectric layer is then formed over the first portion and drain contact vias, which are filled with conductive material, extend therethrough down to drain regions. By having the source regions coupled together with conductive lines within the initial dielectric layer, a low resistance Vss or common source is formed without negatively impacting the word line-to-word line spacing.